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S5K437CX
(1/4" VGA CMOS Image Sensor) DATA SHEET
Revision 1.1
DOCUMENT TITLE
1/4" Optical Size 640 x 480 (VGA) 2.8V CMOS Image Sensor
REVISION HISTORY
Revision No. 0.0 1.0 Initial Draft Changed the operation frequency (30MHz 24.54MHz). Added the shutter operation range limit. Added recommended value for selection of OB_AREA. Added CHIP pad description. 1.1 Added AC characteristic timing diagram (include Standby timing diagram) July, 15. 2004 History Draft Date Mar, 01. 2004 May, 18. 2004 Remark
Table of Contents
Introduction .................................................................................................................................................................2 Features ......................................................................................................................................................................2 Products ......................................................................................................................................................................2 Block Diagram.............................................................................................................................................................3 Pixel Array...................................................................................................................................................................4 Chip Pad Configuration...............................................................................................................................................5 Chip Pad Description ..................................................................................................................................................6 Package Pin Configuration (48 CLCC, Test Only) .....................................................................................................7 Package Pin Description (48CLCC, Test Only) ..........................................................................................................8 Maximum Absolute Limit.............................................................................................................................................9 Electrical Characteristics .......................................................................................................................................10 Control Registers ......................................................................................................................................................13 Operation Description ...............................................................................................................................................18 Timing Chart..............................................................................................................................................................25 Vertical Timing Diagram ........................................................................................................................................25 48CLCC Package Dimension (Test Only) ................................................................................................................29
List of Figures
Figure Number Title Page Number
Figure 1. Block Diagram ............................................................................................................................................. 3 Figure 2. Pixel Array Configuration............................................................................................................................. 4 Figure 3. Pin Configuration......................................................................................................................................... 7 Figure 4. WOI definition ............................................................................................................................................ 18 Figure 5. Bayer Space Sub-Sampling Examples ..................................................................................................... 19 Figure 6. Relative Channel Gain .............................................................................................................................. 20 Figure 7. Relative Global Gain ................................................................................................................................. 21 Figure 8. Recommended Minimum Global Gain Control Value ............................................................................... 21 Figure 9. Quadrisectional Global Gain Control......................................................................................................... 22 Figure 10. I2C Bus Write Cycle ................................................................................................................................. 23 Figure 11. I2C Bus Read Cycle................................................................................................................................. 24
1/4 INCH VGA CMOS IMAGE SENSOR
S5K437CX
INTRODUCTION
S5K437CX is a highly integrated single chip CMOS image sensor developed by SAMSUNG with the 0.35m CMOS image sensor process technology. It is designed to implement high-efficient and low-power photo sensor in the imaging application. The sensor has 640 x 480 effective pixels with 1/4 inch optical format. The sensor digitizes the pixel output with the on-chip 10-bit ADC blocks and drastically Fixed Pattern Noise (FPN) with the onchip CDS. With the interface signals and 10-bit raw data directly connected to the external devices, you can easily set up the camera system. S5K437CX is suitable for low power camera module with 2.8V power supply.
FEATURES
* * * * * * * * * * * * * * * * Process Technology: 0.35m DPTM CMOS Optical Size: 1/4 inch Unit Pixel: 5.6 m X 5.6 m Effective Resolution: 640X480, VGA Line Progressive Read Out. 10-bit Raw Image Data Output Programmable Exposure Time Programmable Gain Control Auto Dark Level Compensation Windowing and Panning Sub-Sampling (2X, 3X, 4X) Standby-Mode for Power Saving Maximum 30 Frame per Second Bad Pixel Replacement Single Power Supply Voltage: 2.8V Package Type: 48-CLCC (TEST Only)
PRODUCTS
Product Code S5K437CX01 S5K437CX02 S5K437CX03 Power Supply 2.8 V 2.8 V 2.8 V Backend Process None On-chip micro lens On-chip color filter and micro lens Description Monochrome image sensor High sensitivity monochrome image sensor RGB color image sensor
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1/4 INCH VGA CMOS IMAGE SENSOR
S5K437CX
BLOCK DIAGRAM
VDDIO VSSIO
VDDD VSSD
MCLK
Main Clock Divider
10-bit Column ADC Odd Column CDS
RSTN STBYN STRB VSYNC HSYNC DCLK
VDDA VSSA
Row Driver
Active Pixel Sensor Array
Control Registers SCL SDA
Even Column CDS 10-bit Column ADC
I2C Interface
Figure 1. Block Diagram
3
Post Processing
Timing Generator
DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
1/4 INCH VGA CMOS IMAGE SENSOR
S5K437CX
PIXEL ARRAY
(Top view on chip. Displayed image will be flipped.)
Active Pixels
Optical Black Pixels
8 6
Default Window of Interest 640X480 G R G R G R G R B G B G B G B G G R G R G R G R B G B G B G B G G R G R G R G R B G B G B G B G G R G R G R G R B G B G B G B G G R G R G R G R B G B G B G B G G R G R G R G R B G B G B G B G
4
4
(14,14) read out start point 6 8
(10,0)
Figure 2. Pixel Array Configuration
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1/4 INCH VGA CMOS IMAGE SENSOR
S5K437CX
CHIP PAD CONFIGURATION
5
1
38
34 33
6
29 Effective Pixel Area (640X480) 28 13
24 CHIP ID (0,0) 14 23
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1/4 INCH VGA CMOS IMAGE SENSOR
S5K437CX
CHIP PAD DESCRIPTION
Pin No VDDD (18) VSSD (1) VDDIO (19,28) VSSIO (29,38) VDDA (4,15,27,30) VSSA (2,3,16,17,25,26,31 ,32) MCLK (37) RSTN (34) STBYN (33) DATA0~DATA9 (5~14) DCLK (20) HSYNC (21) VSYNC (22) SCL (36) SDA (35) TEST1 (23) I/O Power Power Power Power Power Power Analog power supply supply I/O power supply Name Digital power 0V (GND) For I/O circuit ( VDD 10% ) 0V (GND) For analog circuit ( VDD 10% ) 0V (GND) Function For logical circuit ( VDD 10% )
I I I O O O O I I/O I
Master clock Reset Standby Image data output Data clock Horizontal sync clock Vertical sync clock Serial interface clock Serial interface data Test input 1
Master clock pulse input for all timing generators. Initializing all the device registers. (Active low) Activating power saving mode. (high = normal operation, low = power saving mode) 10-bit image data outputs. When ADC resolution is reduced, the unused lower bits are set to 0. Image data output synchronizing pulse output. Horizontal synchronizing pulse or data valid signal output. Vertical synchronizing pulse or line valid signal output. I2C serial interface clock input I2C serial interface data bus (external pull-up resistor required) Test input signal. Though it can be opened in normal operation (internally pulled down), it is recommended to ground the test pins. Test input signal. Though it can be opened in normal operation (internally pulled down), it is recommended to ground the test pins.
TEST2 (24)
I
Test input 2
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1/4 INCH VGA CMOS IMAGE SENSOR
S5K437CX
PACKAGE PIN CONFIGURATION (48 CLCC, TEST ONLY)
DATA0
VSSIO
MCLK
VDDA
VSSD
6 (NC) (NC) DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 (NC) (NC 7 8 9 10 11 12 13 14 15 16 17 18
5
4
3
2
1
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 STBYN VSSA VSSA VDDA VSSIO (NC) (NC) VDDIO VDDA VSSA VSSA TEST2
First Readout Pixel
RSTN 33 32 31 TEST1
VSSA
VSSA
(NC)
(NC)
19 20 21 22 23 24 25 26 27 28 29 30 HSYNC VSYNC DATA9 VDDIO VDDD VSSA VSSA VDDA DCLK (NC) (NC)
Figure 3. Pin Configuration
7
SDA
SCL
1/4 INCH VGA CMOS IMAGE SENSOR
S5K437CX
PACKAGE PIN DESCRIPTION (48CLCC, TEST ONLY)
Pin No VDDD (24) VSSD (1) VDDIO (26,35) VSSIO (38,47) VDDA (4,21,34,39) VSSA (2,3,22,23,32,33,40 ,41) MCLK (46) RSTN (43) STBYN (42) DATA0~DATA9 (6,9 ~ 16,19) DCLK (27) HSYNC (28) VSYNC (29) SCL (45) SDA (44) TEST1 (30) I/O Power Power Power Power Power Power Analog power supply I/O power supply Name Digital power supply Function For logical circuit ( VDD 10% ) 0V (GND) For I/O circuit ( VDD 10% ) 0V (GND) For analog circuit ( VDD 10% ) 0V (GND)
I I I O O O O I I/O I
Master clock Reset Standby Image data output Data clock Horizontal sync clock Vertical sync clock Serial interface clock Serial interface data Test input 1
Master clock pulse input for all timing generators. Initializing all the device registers. (Active low) Activating power saving mode. ( high=normal operation, low=power saving mode ) 10-bit image data outputs. When ADC resolution is reduced, the unused lower bits are set to 0. Image data output synchronizing pulse output. Horizontal synchronizing pulse or data valid signal output. Vertical synchronizing pulse or line valid signal output. I2C serial interface clock input I2C serial interface data bus (external pull-up resistor required) Test input signal. Though it can be opened in normal operation (internally pulled down), it is recommended to ground the test pins. Test input signal. Though it can be opened in normal operation (internally pulled down), it is recommended to ground the test pins.
TEST2 (31)
I
Test input 2
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1/4 INCH VGA CMOS IMAGE SENSOR
S5K437CX
MAXIMUM ABSOLUTE LIMIT
Characteristic Operating voltage (VDDD, VDDIO, VDDA supply related to VSSD, VSSIO, VSSA, VBBA) Input voltage Operating temperature Storage temperature VDD VIN TOPR TSTG -0.3 to VDD+0.3 (Max. 3.8) -20 to +60 -40 to +125(1) -40 to +85(2)
NOTES: 1. Storage temperature tolerance for S5K437C(L)X01. 2. Storage temperature tolerance for S5K437C(L)X02 and S5K437C(L)X03.
Symbol
Value -0.3 to 3.8
Unit V
C
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1/4 INCH VGA CMOS IMAGE SENSOR
S5K437CX
ELECTRICAL CHARACTERISTICS DC Characteristics (TA = -20 to +60C, CL = 15pF) Characteristics Operating voltage Input voltage (1) Input leakage current(2) Input leakage current with pull-down(3) High Level Output voltage (4) Low Level Output voltage (5) High-Z output leakage current (6) Supply current IOZ ISTB IDD Symbol VDD VIH VIL IIL IILD VOH Condition VDDD, VDDIO, VDDA VIN = VDD to VSS VIN = VDD IOH = -1A IOH = -4mA VOL IOL = 1A IOL = 4mA VOUT = VDD STBYN = Low(Active) All input clocks = Low fmclk = 24.54MHz 0 lux illumination
NOTES: 1. Applied to MCLK, RSTN, STBYN, STRB, SCL, SDA, TEST1, TEST2 pin. 2. MCLK, RSTN, STBYN, STRB, SCL, SDA pin 3. TEST1, TEST2 pin 4. DCLK, HSYNC, VSYNC, DATA0 to DATA9 pin 5. DCLK, HSYNC, VSYNC, DATA0 to DATA9, SCL, SDA pin 6. SDA pin when in High-Z output state
Min 2.55 0.8VDD 0 -10 10 VDD0.05 2.4 -
Typ 2.8 30 18
Max 3.05 0.2VDD 10 60 0.05 0.4 10 10 -
Unit V
A
V
A A mA
VDD = 2.8V
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1/4 INCH VGA CMOS IMAGE SENSOR
S5K437CX
Imaging Characteristics (Light source with 3200K of color temperature and IR cut filter (CM-500S, 1mm thickness) are used. It is recommended that the sensor should operate in compliance to the following typical values. The control registers are set to the default values. TA = 25C unless otherwise specified.) Characteristics Saturation level(1) Sensitivity(2) Symbol VSAT S Condition S5K437CX S5K437CX01 S5K437CX02 S5K437CX03 Dark level(3) VDARK TA = 40C TA = 60C Dynamic range(4) Signal to noise ratio(5) Dark signal nonuniformity(6) Photo response nonuniformity(7) Vertical fixed pattern noise(8) Horizontal fixed pattern noise(9) DR S/N DSNU PRNU VFPN HFPN TA = 60C Min 850 Typ 900 1500 4000 1500 9 50 60 40 4 4 4 Max 18 100 100 8 8 8 mV/sec % % % dB mV/sec Unit mV mV/ lux sec
NOTES: 1. Minimum output level measured at 100 lux illumination for exposure time 1/30 sec. 7X7 rank filter is applied to the whole pixel area to eliminate the values from defective pixels. 2. Average output measured at 25% of saturation level illumination for exposure time 1/30 sec. Green channel output values are used for color version. 3. Average output measured at zero illumination without any offset compensation for exposure time 1/30 sec. 4. 20 log (saturation level/ dark level rms noise excluding fixed pattern noise). 60dB is limited by 10-bit ADC. 5. 20 log (average output level/rms noise excluding fixed pattern noise) at 25% of saturation level illumination for exposure time 1/30 sec. 6. Difference between maximum and minimum pixel output levels at zero illumination for exposure time 1/30 sec. 7X7 median filter is applied to the whole pixel area to eliminate the values from defective pixels. 7, Difference between maximum and minimum pixel output levels divided by average output level at 25% of saturation level illumination for exposure time 1/30 sec. 7X7 median filter is applied to the whole pixel area to eliminate the values from defective pixels. 8. For the column-averaged pixel output values, maximum relative deviation of values from 7-depth median filtered values for neighboring 7 columns at 25% of saturation level illumination for exposure time 1/30 sec. 9. For the row-averaged pixel output values, maximum relative deviation of values from 7-depth median filtered values for neighboring 7 columns at 25% of saturation level illumination for exposure time 1/30 sec.
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1/4 INCH VGA CMOS IMAGE SENSOR
S5K437CX
AC Characteristics (VDD = 2.55V to 3.05V for S5K437CX, Ta = -20 to + 60 C, CL = 50pF) Characteristic Main input clock frequency Data output clock frequency Propagation delay time from main input clock Symbol fMCLK fDCLK tPDMV tPDMH tPDMD tPDMO Propagation delay time from data output clock tPDDV tPDDH tPDDO Reset input pulse width Standby input pulse width tWRST tWSTB Condition Duty = 50% VSYNC output HSYNC output DCLK output DATA output VSYNC output HSYNC output DATA output RSTN = low (active) STBYN = low (active) Min 4
(1)
Typ 12 6 -
Max 24.54
(3)
Unit MHz
2 5 4
12.27 20 20 15 20 10 5 5 TMCLK(2) ns
NOTES: 1. 8-bit ADC resolution case. If 10-bit ADC resolution is used, the frequency should be over 12MHz. 2. The period time of main input clock, MCLK.
MCLK
0.5VDD tPDMD
tPDMD DCLK tPDDO DATA tPDMO tPDDH HSYNC tPDMH tPDDV
tPDDH
tPDMH
VSYNC
tPDMV
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1/4 INCH VGA CMOS IMAGE SENSOR
S5K437CX
MCLK tWRST RSTN tWSTB
STBYN system reset partial power down complete power down
I2C Serial Interface Characteristics Characteristic Clock frequency Clock high pulse width Clock low pulse width Clock rise/fall time Data set-up time Data hold time START condition hold time STOP condition setup time STOP to new START gap Capacitance for each pin Capacitive bus load Pull-up resistor Symbol fSCK tWH tWL tR/tF tDS tDH tSTH tSTS tGSS CPIN CBUS RPU SCL, SDA SCL, SDA SCL, SDA to VDD SCK SCK SCK, SDA SDA to SCK SDA to SCK Condition Min 800 1000 300 1200 4 4 8 1.5 4 200 10 k pF Typ Max 400 300 TMCLK Unit kHz ns
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1/4 INCH VGA CMOS IMAGE SENSOR
S5K437CX
CONTROL REGISTERS
Addres s (Hex) 00h Reset Value 02h Bits [5] [4] [3] [2] [1:0] 01h 10h [7] [6] [5:4] Mnemonic bprm Not use ccsm shutc adcres mircv mirch mcdiv Color channel separation mode 0b: not separated (default), 1b: separated Electronic shutter mode 0b: disabled (default), 1b: enabled ADC resolution 00b: 8-bit, 01b: 9-bit, 10b: 10-bit (default) Vertical mirror control 0b: normal (default), 1b: mirrored Horizontal mirror control 0b: normal (default), 1b: mirrored Main clock divider 00b: DCLK=MCLK, 01b: DCLK=MCLK/ 2 (default) 10b: DCLK=MCLK/ 4, 11b: DCLK=MCLK/ 8 [3:2] subsr Row subsampling mode 00b: disabled (default), 01b: 2X, 10b: 3X, 11b: 4X [1:0] subsc Column subsampling mode 00b: disabled (default), 01b: 2X, 10b: 3X, 11b: 4X 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 00h 0Eh 00h 0Eh 01h E0h 02h 80h 80h [0] [7:0] [0] [7:0] [0] [7:0] [1:0] [7:0] [7:0] wrp_high wrp_low wcp_high wcp_low wrd_high wrd_low wcw_high wcw_low Row start point for window of interest wrp[8:0] = 14d(default) Column start point for window of interest wcp[8:0] = 14d(default) Row depth for window of interest wrd[8:0] = 480d(default) Column width for window of interest wcw[9:0] = 640d(default) (Factory use only) Description Bad pixel replacement mode 0b: disabled (default), 1b: enabled
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1/4 INCH VGA CMOS IMAGE SENSOR
S5K437CX
Addres s (Hex) 0Dh 0Eh 0Fh 10h 11h 12h
Reset Value 01h 06h 00h 00h 01h 00h
Bits [4:0] [7:0] [5:0] [7:0] [7:0] [5] [4] [1:0]
Mnemonic cintr_high cintr_low cintc_high cintc_low vswd vspolar vsdisp vsstrt_high vsstrt_low vblank_high vblank_low hswd hspolar hsdisp hsstart_high hsstart_low hblank_high hblank_low
Description Row-step integration time in continuous frame capture mode (range is described in operation description) cintr[12:0] = 262d (default) Column-step integration time in continuous frame capture mode (range is described in operation description) cintc[13:0] = 0d (default) VSYNC width vswd[7:0] = 1d (default) VSYNC polarity 0: active high (default), 1: active low VSYNC display mode 0: sync mode (default), 1: data valid mode VSYNC start position vsstrt[9:0] = 0d (default) Vertical blank depth vblank[12:0] = 45d (default) HSYNC width hswd[7:0] = 32d (default) HSYNC polarity 0: active high (default), 1: active low HSYNC display mode 0: sync mode (default), 1: data valid mode HSYNC start position hsstrt[9:0] = 0d (default) Horizontal blank depth hblank[13:0] = 140d (default)
13h 14h 15h 16h 17h
00h 00h 2Dh 20h 00h
[7:0] [4:0] [7:0] [7:0] [5] [4] [1:0]
18h 19h 1Ah
00h 00h 8Ch
[7:0] [5:0] [7:0]
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1/4 INCH VGA CMOS IMAGE SENSOR
S5K437CX
Addres s (Hex) 1Bh
Reset Value 77h
Bits [3:0] [7:4]
Mnemonic sgg1 sgg2 sgg3 sgg4 pgcr pgcg1
Description 1st quadrisectional global gain 7d (default) 2nd quadrisectional global gain 7d (default) 3rd quadrisectional global gain 15d (default) 4th quadrisectional global gain 15d (default) Red channel gain pgcr[6:0] = 0d (default) Green(Red row) channel gain or all channel gain (ccsm = 0) pgcg1[6:0] = 0d (default) Green(Blue row) channel gain pgcg2[6:0] = 0d (default) Blue channel gain pgcb[6:0] = 0d (default) Red channel analog offset Offsr[7:0] = 128 (default) Green(Red row) channel analog offset or all channel offset (ccsm=0) offsg1[7:0] = 128 (default) Green(Blue row) channel analog offset offsg2[7:0] = 128 (default) Blue channel analog offset offsb[7:0] = 128 (default) Bad pixel threshold pthresh[6:0] = 20d (default) ADC offset adcoffs[7:0] = 0d (default)
1Ch
77h
[3:0] [7:4]
1Dh 1Eh
00h 00h
[6:0] [6:0]
1Fh 20h 21h 22h
00h 00h 80h 80h
[6:0] [6:0] [7:0] [7:0]
pgcg2 pgcb offsr offsg1
23h 24h 25h 26h
80h 80h 14h 00h
[7:0] [7:0] [6:0] [7:0]
offsg2 offsb pthresh adcoffs
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1/4 INCH VGA CMOS IMAGE SENSOR
S5K437CX
Addres s (Hex) 27h
Reset Value 0Ch
Bits [5] [4] [3:0]
Mnemonic (Factory use only) NOT USE (Factory use only) (Factory use only) (Factory use only) (Factory use only) blank
Description
28h 29h 2Ah 2Bh
40h 00h 00h 02h
[7:5] [4:0] [7:0] [7:0] [7:6] [5] [4] [3] [2] [1] [0]
Blank register for general purpose (Factory use only) (Factory use only) (Factory use only) (Factory use only) (Factory use only) (Factory use only) (Factory use only)
2Ch
00h
[7] [6] [5] [4] [3:2]
adlc_mod_d adlc_mod_c adlc_mod_b adlc_mod_a feedback_gain_B
Adlc mode always enable when 0b: disabled (default), 1b: enabled Adlc mode works when gain value is changed 0b: disabled (default), 1b: enabled Adlc mode works when shutter value is changed 0b: disabled (default), 1b: enabled Adlc mode works till adlc length value 0b: disabled (default), 1b: enabled Feedback gain value about ADLC ADLC formula : Dnew = A*(OBold + OBnew) + B*Dold 00b : 0 (default), 01b : 0.5, 10b : 0.75, 11b : 1
[1:0]
feedback_gain_A
Feedback gain value about ADLC 00b : 0 (default), 01b : 0.5, 10b : 0.25, 11b : 0.125
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1/4 INCH VGA CMOS IMAGE SENSOR
S5K437CX
Addres s (Hex) 2Dh
Reset Value 10h
Bits [7] [6] [5] [4] [3]
Mnemonic mckout_en b2 b1 b0 OB_sel DCK pad control
Description
0b : stable value (default), 1b : output enable I/O driver fan-out control register. {b2, b1, b0} = {001} (1/3), {011} (2/3), {111} (3/3) ADLC formura : Dnew = A*(OBold + OBnew) + B*Dold 0b : OBold = OBold (default) 1b : OBold = OBnew [2] [1:0] OB_area adlc_length OB area selection 0b : 128 * 8 (default), 1b : 512*2 (recommend) ADLC function works only during this value when adlc_mod_a enabled, 00b : 1 frame, 01b : 2 frames, 10b : 3 frames, 2Eh 2F CCh 0Ch [7:4] [3:0] [4] [3:0] tg_sel 11b : 4 frames (Factory use only) (Factory use only) Pixel TG signal selection 0b: disabled (default), 1b: enabled (Factory use only
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1/4 INCH VGA CMOS IMAGE SENSOR
S5K437CX
OPERATION DESCRIPTION
1. Output Data Format 1-1. Main Clock Divider All the data output and sync signals are synchronized to data clock output (DCLK). It is generated as the main clock input (MCLK) is divided. The dividing ratio is 1, 2, 4, and 8 according to main clock dividing control register (mcdiv). For 10-bit ADC and VGA resolution, dividing ratio of more than 2 is required. If ratio of 1 is used, the duty must be within 40% to 60%. 1-2. Synchronous Signal Output The horizontal sync (HSYNC) and vertical sync (VSYNC) signals are also available. The sync pulse width, polarity and position are programmable on the control registers (ref. timing chart). When display mode is activated, the sync signal outputs indicate that the output data is valid (hsdisp = 1) or the output rows are valid (vsdisp = 1). 1-3. Window of Interest Control Window of Interest (WOI) is defined as the pixel address range to be read out. The WOI can be assigned anywhere on the pixel array. It is composed of four values: row start pointer (wrp), column start pointer (wcp), row depth(wrd) and column width (wcw). Each value can be programmed on the control registers. For convenience of color signal processing, wcp is truncated to even numbers so that the starting data of each line is on the red and green column of Bayer pattern. Figure 4 illustrates the WOI on the displayed pixel image.
0 (wcp,wrp)
687 wcw
Window Of Interest wrd 507
Figure 4. WOI definition 1-4. Vertical Mirror and Horizontal Mirror Mode Control The pixel data are normally read out from left to right in horizontal direction and from top to bottom in vertical direction. By changing the mirror mode, the read-out sequence can be reversed and the resulting image can be flipped like a mirror image. Pixel data are read out from right to left in horizontal mirror mode and from bottom to top in vertical mirror mode. The horizontal and the vertical mirror mode can be programmed on the Horizontal Mirror Control Register (mirch) and Vertical Mirror Control Register (mircv). 1-5. Sub-sampling Control The pixel data in sub-sampling rate can be read out in both horizontal and vertical direction. Sub-sampling can be done in four rates : full, 1/2, 1/3 and 1/4. You can control the sub-sampling on the Sub-sampling Control Registers, subsr and subsc. The sub-sampling is performed only in the Bayer space.
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1/4 INCH VGA CMOS IMAGE SENSOR
S5K437CX
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
subsr = 01b, subsc = 01b
subsr = 00b, subsc = 11b
Figure 5. Bayer Space Sub-Sampling Examples 1-6. Line Rate and Frame Rate Control (Virtual Frame) The line rate and the frame rate vary depending on the size of virtual frame. The virtual frame width and depth are controlled to effective WOI and blank depths. The effective WOI is scaled by the subsampling factors from WOI set by register values. For CDS and ADC function, the virtual column width must be larger than (adcres+1)*256/(2^mcdiv)+110, where adcres is the ADC resolution control register value. The resulting frame time and line time which are inverse of frame rate and line rate are represented by following equations: 1 frame time = { wrd / (subsr+1) + vblank } * (1 line time) 1 line time = { wcw / (subsc+1) + hblank } * (DCLK period) 1-7. Continuous Frame Capture Mode(CFCM) Integration Time Control (Electronic Shutter Control) In CFCM operation, the integration time is controlled by shutter operation. The shutter operation is done when shutter control register (shutc) is set to '1'. In shutter operation, the integration time is determined by the Row Step Integration Time Control Register(cintr) and Column Step Integration Time Control Register(cintc). The resulting integration time is expressed as; Integration Time = (cintr - 1) * (1 line time) + (cintc +110) * (DCLK period) where cintr = 1 to { wrd / (subsr+1) + vblank }, case of ( 1<= cintr <= {wrd / (subsr+1) + vblank -1} ) 0 <= cintc <= { wcw / (subsc+1) + hblank -44 }. case of ( cintr = { wrd / (subsr+1) + vblank }, 0 <= cintc <= { wcw / (subsc+1) + hblank -205} 1-8. Single Frame Capture Mode(SFCM) Integration Time Control To capture a still image, SFCM should be set by Single Frame Capture Enable Register(sfcen). There are two types of integration mode implemented. In the rolling shutter mode (sfcim = 0), the integration time is controlled by SFCM Integration Time Register (sint). The light integration period for each rows progresses with reading rows. The integration time is expressed as : Integration Time = sint * (1 line time) In the mechanical shutter mode (sfcim = 1), the integration time for all rows is the period during which the external input signal, STRB is active. After STRB gets inactivated, the external mechanical shutter should shut off incident light on image sensor, and then, the data readout sequence starts.
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1/4 INCH VGA CMOS IMAGE SENSOR
S5K437CX
2. Analog to Digital Converter ( ADC) The image sensor has an on-chip ADC. Two-channel column parallel ADC scheme is used for separated color channel gain and offset control. 2-1. ADC resolution The default value of ADC resolution is 10bit and can be changed to 8-bit or 9-bit depending on the ADC Resolution Control Register (adcres). Lowering ADC resolution reduces the required minimum line time. When the number of effective output bits is reduced, upper n-bits of output ports are valid and lower bits always have the value of '0'. 2-2. Correlated Double Sampling (CDS) The analog output signal of each pixel has some temporal random noise and fixed pattern noise caused by the pixel reset action and the in-pixel amplifier offset deviation respectively. To eliminate those noise components, a correlated double sampling(CDS) circuit should be used before converting the mode to digital. The output signal is sampled twice - one for the reset level and one for the actual signal level sampling. 2-3. Programmable Gain and Offset Control You can control the gain of individual color channel on the Programmable Gain Control Registers (pgcr, pgcg1, pgcg2, pgcb) and offset on Offset Control Registers (offsr, offsg1, offsg2, offsb). If the Color Channel Separation Mode is disabled (ccsm=0), pgcg1 and offsg1 change the gains and offsets for all channels. As the value increases on the gain control register, the ADC conversion input range decreases and the gain increases as shown in the following equation:
R G1 R G1 G2 B G2 B R G1 R G1 G2 B G2 B
10 9 Relative Channel Gain 8 7 6 5 4 3 2 1 0 16 32 48 64 80 96 112 128 Programmable Gain Control Channel Gain (dB)
45 40 35 30 25 20 15 10 5 0 0 16 32 48 64 80 96 112 128 Programmable Gain Control
Channel Gain = 128 / (128 Programmable Gain Control Register Value[6:0]) Figure 6. Relative Channel Gain
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1/4 INCH VGA CMOS IMAGE SENSOR
S5K437CX
2-4. Quadrisectional Global Gain Control You can control the global gain to change the gain for all color channels on the Global Gain Control Registers (sgg1, sgg2, sgg3, sgg4). The global gain control register is composed of four register groups and each register value decides the gain for each quarter section of output code level. Global Gain = (sgg[3:0]+1) / 8
2.0 1.8 1.6 Relative Global Gain Glabal Gain (dB) 0 2 4 6 8 10 12 14 16 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 Programmable Gain Control -20 0 2 4 6 8 10 12 14 16 Programmable Gain Control 5 0 -5 -10 -15 10
Figure 7. Relative Global Gain The ADC gain is dependent on MCLK frequency (not on DCLK frequency) and ADC resolution. The default global gain is set for typical MCLK frequency (24.54MHz) and 10-bit ADC. When the frequency and ADC resolution are changed, the global gain should be changed in order that the resulting gain should be maintained over unity to ensure appropriate ADC conversion range.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8
Minimum Glabal Gain
10-bit ADC resolution
9-bit ADC resolution 8-bit ADC resolution
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MCLK frequency (MHz)
Figure 8. Recommended Minimum Global Gain Control Value
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1/4 INCH VGA CMOS IMAGE SENSOR
S5K437CX
By appropriately programming these four register values, you can acquire different output resolutions depending on the signal and can increase the intra-scene dynamic range by 16 times. In another application, the sectional global gain control can be used as a rough gamma correction with four sectional linear approximation curves as shown in Figure 9.
sgg1 ADC input signal
sgg2
sgg3
sgg4
sgg1=1111b sgg3=0011b sgg2=0111b sgg4=0000b
sgg1=0111b sgg2=0111b sgg3=0111b sgg4=0111b
0
255
511
767
1023
ADC output code at 10-bit resolution
Figure 9. Quadrisectional Global Gain Control 3. Post Processing 3-1. Auto Dark Level Compensation(ADLC) The dark level of Image sensor means the average output level without illumination. It includes pixel output caused by leakage current of the photodiodes and ADC offset. To compensate the dark level, the output level of optical black(OB) pixels should be in a good reference value. Auto Dark Level Compensation has 4 operating modes. ADLC mode A only works for (adlc_length +1) frame time. ADLC mode B only works when the change of shutter values is detected at the start of each frame. ADLC mode C only works when the change of channel gain values is detected at the start of each frame. ADLC mode D works always when this register is set to high. When ADLC mode is activated, the image sensor detects the OB pixel level, optionally 512X2 or 128X8, at the start of the enabled frame, and analog-to-digital conversion range is shifted to compensate the dark level for that frame. So, the resulting output data of that frame will be almost zero under dark state. You can select the dark level which is not zero on the ADC Offset Register (adcoffs). The lower 7-bit value represents the offset value in output code for compensation and the MSB shows whether the offset is positive (adcoffs[7]=0) or negative (adcoffs[7]=1). When not in auto dark level compensation mode, the adcoffs[7:0] act as a output code value to subtract the output image data. Please note that all the 8-bit data are used for an offset value without a sign bit. The resulting ADLC value is expressed as; ADLCcurrent = * (OBold + OBnew) + * ADLCold ( is set by register feedback_gain_A , is set by register feedback_gain_B)
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1/4 INCH VGA CMOS IMAGE SENSOR
S5K437CX
3-2. Bad Pixel Replacement If the Bad Pixel Replacement Register (bprm) is disabled, the image sensor checks, with the preset threshold value (pthresh), if the image data is less or greater than horizontally neighboring pixels in same color channel. If satisfied, the output of the pixel is replaced by the averaged value of the neighboring two pixels. The detectable defective pixels are rare and the bad pixel replacement action can remove the defective image effectively. But it reduces the line resolution in the horizontal direction. 4. I2C Serial Interface I2C is an industry standard serial interface. I2C contains a serial two-wire half duplex interface that features bidirectional operation, master or slave mode. The general SDA and SCL are the bi-directional data and clock pins, respectively. These pins are open-drain type ports and will require a pull-up resistor to VDD. The image sensor operates in the salve mode only and the SCL is input only. I2C bus interface is composed of following parts : START signal, 7-bit slave device address (0010001b) transmission followed by a read/write bit, an acknowledgement signal from the slave, 8-bit data transfer followed by an acknowledgement signal and STOP signal. The SDA bus line may only be changed while SCL is low. The data on the SDA bus line is valid on the high-to-low transition of SCL.
SCL SDA
"0" "0" "1" "0" "0" "0" "1"
D7 I2C Bus Address
D6
D5
D4
D3
D2
D1
D0
start
Write Ack
I2C Register Address
Ack
SCL SDA D7 D6 D5 D4 D3 D2 D1 D0
Data to Write
Ack Stop
Figure 10. I2C Bus Write Cycle
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1/4 INCH VGA CMOS IMAGE SENSOR
S5K437CX
SCL SDA
"0" "0" 1 "0" "0" "0" 1
D7 I 2C Bus Address
D6
D5
D4
D3
D2
D1
D0
X
Start SCL SDA
"0" "0"
Write Ack
I2C Register Address
Ack
D7
"1" "0" "0" "0" "1"
D6
D5
D4
D3
D2
D1
D0
Re-Start
I2C Bus Address
Read Ack
Data to be Read
Ack Stop
Figure 11. I2C Bus Read Cycle
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1/4 INCH VGA CMOS IMAGE SENSOR
S5K437CX
TIMING CHART
VERTICAL TIMING DIAGRAM Continuous Frame Capture Mode (Default Case)
1 frame = wrd + vblank (525 rows ) VSYNC vswd (1row) HSYNC
DATA wrp (14th row) wrd (480 rows) vblank (45rows)
(Delayed Vertical Sync Case)
1 frame = wrd + vblank (525 rows) VSYNC vsstrt vswd
HSYNC
DATA 2 rows 2 rows
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1/4 INCH VGA CMOS IMAGE SENSOR
S5K437CX
(Vertical Data Valid Mode Case) vsdisp = 1
VSYNC HSYNC (hsdisp=0) HSYNC (hsdisp=1)
DATA wrd vblank
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1/4 INCH VGA CMOS IMAGE SENSOR
S5K437CX
Horizontal Timing Diagram (Default Case)
1 row = wcw + hblank ( 780columns) VSYNC HSYNC
hswd 10 (32 DCLK) DCLK
DCLK
DATA wcp (14th column) wcw ( 640 columns ) hblank (140columns)
(Delayed Horizontal Sync Case)
1 row = wcw + hblank VSYNC HSYNC hsstrt DCLK hswd
DATA 42 DCLK wcw 42 DCLK
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1/4 INCH VGA CMOS IMAGE SENSOR
S5K437CX
(Horizontal Data Valid Mode Case ) hsdisp = 1
VSYNC HSYNC
DCLK
DATA 42 DCLK wcw hblank
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1/4 INCH VGA CMOS IMAGE SENSOR
S5K437CX
48CLCC PACKAGE DIMENSION (TEST ONLY)
Center of Image Area (X=+0.50 + 0.15, Y= 0.00 + 0.15 from package center) Max. Chip Rotation = + 1.5 degree Max. Chip Tilt = 0.05mm
14.22SQ + 0.30/-0.13 6 1 48 43 42
TOP VIEW
7
X
Center of Image Area (X = + 0.50 + 0.15, Y = 0.00 + 0.15 from package center) Max. Chip Rotation = + 1.5 degree Max. Chip Tilt = 0.05mm 31
18 19 SIDE VIEW Glass 30
0.55 + 0.05 1.65 + 0.18
11.176 + 0.13 1.016 + 0.08 48 1 BOTTOM VIEW
R 0.15 4 Corners
0.51 + 0.08
1.016 + 0.18
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1/4 INCH VGA CMOS IMAGE SENSOR
S5K437CX
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1/4 INCH VGA CMOS IMAGE SENSOR
S5K437CX
NOTES
2004 Samsung Electronics All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics.
Samsung Electronics Co., Ltd. San #24 Nongseo-Ri, Giheung-Eup Yongin-City, Gyeonggi-Do, Korea C.P.O. Box #37, Suwon 449-900 Homepage: www.samsungsemi.com
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